/*
 **************************************************************************
 * Copyright (c) 2016-2019, 2021, The Linux Foundation. All rights reserved.
 *
 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 **************************************************************************
*/

#ifndef __EDMA_REGS__
#define __EDMA_REGS__

#define IPQ5332_EDMA_CFG_BASE			0x3ab00000

/*
 * IPQ5332 EDMA register offsets
 */
#define IPQ5332_EDMA_REG_MAS_CTRL		0x0
#define IPQ5332_EDMA_REG_PORT_CTRL		0x4
#define IPQ5332_EDMA_REG_RXDESC2FILL_MAP_0	0x14
#define IPQ5332_EDMA_REG_RXDESC2FILL_MAP_1	0x18
#define IPQ5332_EDMA_REG_DMAR_CTRL		0x48
#define IPQ5332_EDMA_REG_MISC_INT_STAT		0x5c
#define IPQ5332_EDMA_REG_MISC_INT_MASK		0x60
#define IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_0	0x8c
#define IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_1	0x90
#define IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_2	0x94
#define IPQ5332_EDMA_REG_TXDESC2CMPL_MAP_3	0x98
#define IPQ5332_EDMA_REG_MDIO_SLV_PASUE_MAP_0	0xA4
#define IPQ5332_EDMA_REG_MDIO_SLV_PASUE_MAP_1	0xA8

#define IPQ5332_EDMA_REG_TXDESC_BA(n)		(0x1000 + (0x1000 * n))
#define IPQ5332_EDMA_REG_TXDESC_PROD_IDX(n)	(0x1004 + (0x1000 * n))
#define IPQ5332_EDMA_REG_TXDESC_CONS_IDX(n)	(0x1008 + (0x1000 * n))
#define IPQ5332_EDMA_REG_TXDESC_RING_SIZE(n)	(0x100c + (0x1000 * n))
#define IPQ5332_EDMA_REG_TXDESC_CTRL(n)		(0x1010 + (0x1000 * n))
#define IPQ5332_EDMA_REG_TXDESC_BA2(n)		(0x1014 + (0x1000 * n))

#define IPQ5332_EDMA_REG_RXFILL_BA(n)		(0x29000 + (0x1000 * n))
#define IPQ5332_EDMA_REG_RXFILL_PROD_IDX(n)	(0x29004 + (0x1000 * n))
#define IPQ5332_EDMA_REG_RXFILL_CONS_IDX(n)	(0x29008 + (0x1000 * n))
#define IPQ5332_EDMA_REG_RXFILL_RING_SIZE(n)	(0x2900c + (0x1000 * n))
#define IPQ5332_EDMA_REG_RXFILL_RING_EN(n)	(0x2901c + (0x1000 * n))
#define IPQ5332_EDMA_REG_RXFILL_INT_STAT(n)	(0x31000 + (0x1000 * n))
#define IPQ5332_EDMA_REG_RXFILL_INT_MASK(n)	(0x31004 + (0x1000 * n))

#define IPQ5332_EDMA_REG_RXDESC_BA(n)		(0x39000 + (0x1000 * n))
#define IPQ5332_EDMA_REG_RXDESC_PROD_IDX(n)	(0x39004 + (0x1000 * n))
#define IPQ5332_EDMA_REG_RXDESC_CONS_IDX(n)	(0x39008 + (0x1000 * n))
#define IPQ5332_EDMA_REG_RXDESC_RING_SIZE(n)	(0x3900c + (0x1000 * n))
#define IPQ5332_EDMA_REG_RXDESC_FC_THRE(n)	(0x39010 + (0x1000 * n))
#define IPQ5332_EDMA_REG_RXDESC_CTRL(n)		(0x39018 + (0x1000 * n))
#define IPQ5332_EDMA_REG_RXDESC_BA2(n)		(0x39028 + (0x1000 * n))
#define IPQ5332_EDMA_REG_RXDESC_INT_STAT(n)	(0x59000 + (0x1000 * n))
#define IPQ5332_EDMA_REG_RXDESC_INT_MASK(n)	(0x59004 + (0x1000 * n))
#define IPQ5332_EDMA_REG_RX_INT_CTRL(n)		(0x5900c + (0x1000 * n))

#define IPQ5332_EDMA_REG_TXCMPL_BA(n)		(0x79000 + (0x1000 * n))
#define IPQ5332_EDMA_REG_TXCMPL_PROD_IDX(n)	(0x79004 + (0x1000 * n))
#define IPQ5332_EDMA_REG_TXCMPL_CONS_IDX(n)	(0x79008 + (0x1000 * n))
#define IPQ5332_EDMA_REG_TXCMPL_RING_SIZE(n)	(0x7900c + (0x1000 * n))
#define IPQ5332_EDMA_REG_TXCMPL_CTRL(n)		(0x79014 + (0x1000 * n))

#define IPQ5332_EDMA_REG_TX_INT_STAT(n)		(0x99000 + (0x1000 * n))
#define IPQ5332_EDMA_REG_TX_INT_MASK(n)		(0x99004 + (0x1000 * n))
#define IPQ5332_EDMA_REG_TX_INT_CTRL(n)		(0x9900c + (0x1000 * n))

/*
 * EDMA QID2RID configuration
 */
#define IPQ5332_EDMA_QID2RID_TABLE_MEM(q)	(0xb9000 + (0x4 * q))

#define IPQ5332_EDMA_CPU_PORT_MC_QID_MIN	256
#define IPQ5332_EDMA_CPU_PORT_MC_QID_MAX	271
#define IPQ5332_EDMA_QID2RID_NUM_PER_REG	4

/*
 * EDMA_REG_DMAR_CTRL register
 */
#define IPQ5332_EDMA_DMAR_REQ_PRI_MASK			0x7
#define IPQ5332_EDMA_DMAR_REQ_PRI_SHIFT			0x0
#define IPQ5332_EDMA_DMAR_BURST_LEN_MASK		0x1
#define IPQ5332_EDMA_DMAR_BURST_LEN_SHIFT		3
#define IPQ5332_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_MASK	0x1f
#define IPQ5332_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SHIFT	4
#define IPQ5332_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_MASK	0x7
#define IPQ5332_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SHIFT	9
#define IPQ5332_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_MASK	0x7
#define IPQ5332_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SHIFT	12

#define IPQ5332_EDMA_DMAR_REQ_PRI_SET(x) (((x) & IPQ5332_EDMA_DMAR_REQ_PRI_MASK) \
					 << IPQ5332_EDMA_DMAR_REQ_PRI_SHIFT)
#define IPQ5332_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SET(x) (((x) & IPQ5332_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_MASK) \
					 << IPQ5332_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SHIFT)
#define IPQ5332_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SET(x) (((x) & IPQ5332_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_MASK) \
					 << IPQ5332_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SHIFT)
#define IPQ5332_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SET(x) (((x) & IPQ5332_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_MASK) \
					 << IPQ5332_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SHIFT)
#define IPQ5332_EDMA_DMAR_BURST_LEN_SET(x) (((x) & IPQ5332_EDMA_DMAR_BURST_LEN_MASK) \
					 << IPQ5332_EDMA_DMAR_BURST_LEN_SHIFT)

#define IPQ5332_EDMA_BURST_LEN_ENABLE			0x0

/*
 * EDMA_REG_PORT_CTRL register
 */
#define IPQ5332_EDMA_PORT_CTRL_EN			0x3

/*
 * EDMA_REG_TXDESC_PROD_IDX register
 */
#define IPQ5332_EDMA_TXDESC_PROD_IDX_MASK		0xffff

/*
 * EDMA_REG_TXDESC_CONS_IDX register
 */
#define IPQ5332_EDMA_TXDESC_CONS_IDX_MASK		0xffff

/*
 * EDMA_REG_TXDESC_RING_SIZE register
 */
#define IPQ5332_EDMA_TXDESC_RING_SIZE_MASK		0xffff

/*
 * EDMA_REG_TXDESC_CTRL register
 */
#define IPQ5332_EDMA_TXDESC_TX_EN			0x1

/*
 * EDMA_REG_TXCMPL_PROD_IDX register
 */
#define IPQ5332_EDMA_TXCMPL_PROD_IDX_MASK		0xffff

/*
 * EDMA_REG_TXCMPL_CONS_IDX register
 */
#define IPQ5332_EDMA_TXCMPL_CONS_IDX_MASK		0xffff

/*
 * EDMA_REG_TX_INT_CTRL register
 */
#define IPQ5332_EDMA_TX_INT_MASK			0x3

/*
 * EDMA_REG_RXFILL_PROD_IDX register
 */
#define IPQ5332_EDMA_RXFILL_PROD_IDX_MASK		0xffff

/*
 * EDMA_REG_RXFILL_CONS_IDX register
 */
#define IPQ5332_EDMA_RXFILL_CONS_IDX_MASK		0xffff

/*
 * EDMA_REG_RXFILL_RING_SIZE register
 */
#define IPQ5332_EDMA_RXFILL_RING_SIZE_MASK		0xffff
#define IPQ5332_EDMA_RXFILL_BUF_SIZE_MASK		0xffff0000
#define IPQ5332_EDMA_RXFILL_BUF_SIZE_SHIFT		16

/*
 * EDMA_REG_RXFILL_RING_EN register
 */
#define IPQ5332_EDMA_RXFILL_RING_EN			0x1

/*
 * EDMA_REG_RXFILL_INT_MASK register
 */
#define IPQ5332_EDMA_RXFILL_INT_MASK			0x1

/*
 * EDMA_REG_RXDESC_PROD_IDX register
 */
#define IPQ5332_EDMA_RXDESC_PROD_IDX_MASK		0xffff

/*
 * EDMA_REG_RXDESC_CONS_IDX register
 */
#define IPQ5332_EDMA_RXDESC_CONS_IDX_MASK		0xffff

/*
 * EDMA_REG_RXDESC_RING_SIZE register
 */
#define IPQ5332_EDMA_RXDESC_RING_SIZE_MASK		0xffff
#define IPQ5332_EDMA_RXDESC_PL_OFFSET_MASK		0x1ff
#define IPQ5332_EDMA_RXDESC_PL_OFFSET_SHIFT		16

/*
 * EDMA_REG_RXDESC_CTRL register
 */
#define IPQ5332_EDMA_RXDESC_RX_EN			0x1

/*
 * EDMA_REG_TX_INT_MASK register
 */
#define IPQ5332_EDMA_TX_INT_MASK_PKT_INT		0x1
#define IPQ5332_EDMA_TX_INT_MASK_UGT_INT		0x2

/*
 * EDMA_REG_RXDESC_INT_MASK register
 */
#define IPQ5332_EDMA_RXDESC_INT_MASK_PKT_INT		0x1
#define IPQ5332_EDMA_MASK_INT_DISABLE			0x0

/*
 * TXDESC shift values
 */
#define IPQ5332_EDMA_TXDESC_DATA_OFFSET_SHIFT		0
#define IPQ5332_EDMA_TXDESC_DATA_OFFSET_MASK		0xfff

#define IPQ5332_EDMA_TXDESC_DATA_LENGTH_SHIFT		0
#define IPQ5332_EDMA_TXDESC_DATA_LENGTH_MASK		0x1ffff

#define IPQ5332_EDMA_DST_PORT_TYPE			2
#define IPQ5332_EDMA_DST_PORT_TYPE_SHIFT		28
#define IPQ5332_EDMA_DST_PORT_TYPE_MASK			(0xf << IPQ5332_EDMA_DST_PORT_TYPE_SHIFT)
#define IPQ5332_EDMA_DST_PORT_ID_SHIFT			16
#define IPQ5332_EDMA_DST_PORT_ID_MASK			(0xfff << IPQ5332_EDMA_DST_PORT_ID_SHIFT)

#define IPQ5332_EDMA_DST_PORT_TYPE_SET(x)		(((x) << IPQ5332_EDMA_DST_PORT_TYPE_SHIFT) & IPQ5332_EDMA_DST_PORT_TYPE_MASK)
#define IPQ5332_EDMA_DST_PORT_ID_SET(x)			(((x) << EDMA_DST_PORT_ID_SHIFT) & EDMA_DST_PORT_ID_MASK)

#define IPQ5332_EDMA_RXDESC_SRCINFO_TYPE_PORTID		0x2000
#define IPQ5332_EDMA_RXDESC_SRCINFO_TYPE_SHIFT		8
#define IPQ5332_EDMA_RXDESC_SRCINFO_TYPE_MASK		0xf000
#define IPQ5332_EDMA_RXDESC_PORTNUM_BITS		0x0FFF

#define IPQ5332_EDMA_RING_DMA_MASK			0xffffffff

/*
 * RXDESC shift values
 */
#define IPQ5332_EDMA_RXDESC_PKT_SIZE_MASK		0x3ffff
#define IPQ5332_EDMA_RXDESC_PKT_SIZE_SHIFT		0
#define IPQ5332_EDMA_RXDESC_SRC_INFO_GET(x)		(x & 0xFFFF)
#define IPQ5332_EDMA_RXDESC_RING_INT_STATUS_MASK	0x3
#define IPQ5332_EDMA_RXFILL_RING_INT_STATUS_MASK	0x1

#define IPQ5332_EDMA_TXCMPL_RING_INT_STATUS_MASK	0x3
#define IPQ5332_EDMA_TXCMPL_RETMODE_OPAQUE		0x0
#define IPQ5332_EDMA_TX_NE_INT_EN			0x2
#define IPQ5332_EDMA_RX_NE_INT_EN			0x2
#define IPQ5332_EDMA_TX_INITIAL_PROD_IDX		0x0

#endif /*  __EDMA_REGS__ */
